AS-SiliconMind/SiliconMind-V1
Inference Engine for SiliconMind-V1 Verilog Coding Models
Leverages multi-agent distillation and iterative test-time scaling to generate, validate, and self-debug Verilog designs without external EDA tools, offering three workflows: regular single-pass generation, deep-thinking with built-in self-review, and agentic loops with reflective debugging. Built on vLLM for high-performance inference with batch processing support and a CLI interface (`slcm`) for immediate use.
Stars
16
Forks
3
Language
Python
License
Apache-2.0
Category
Last pushed
Mar 11, 2026
Commits (30d)
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