AS-SiliconMind/SiliconMind-V1

Inference Engine for SiliconMind-V1 Verilog Coding Models

41
/ 100
Emerging

Leverages multi-agent distillation and iterative test-time scaling to generate, validate, and self-debug Verilog designs without external EDA tools, offering three workflows: regular single-pass generation, deep-thinking with built-in self-review, and agentic loops with reflective debugging. Built on vLLM for high-performance inference with batch processing support and a CLI interface (`slcm`) for immediate use.

No Package No Dependents
Maintenance 13 / 25
Adoption 6 / 25
Maturity 9 / 25
Community 13 / 25

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Stars

16

Forks

3

Language

Python

License

Apache-2.0

Last pushed

Mar 11, 2026

Commits (30d)

0

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