hls4ml and rule4ml
hls4ml compiles ML models to FPGA hardware designs via HLS, while rule4ml estimates the resource and latency costs of those deployments, making them complements that address consecutive stages of the FPGA ML design flow.
About hls4ml
fastmachinelearning/hls4ml
Machine learning on FPGAs using HLS
Automatically converts trained models from Keras, PyTorch, and other frameworks into synthesizable HLS code, supporting multiple vendor backends (Xilinx Vivado/Vitis, Intel, Catapult). Optimizes for sub-microsecond latency inference through techniques like quantization to binary/ternary precision, distributed arithmetic, and CNN/semantic segmentation acceleration. Originally developed for high-energy physics trigger systems but now deployed across quantum control, satellite monitoring, and biomedical signal processing applications.
About rule4ml
IMPETUS-UdeS/rule4ml
Resource Utilization and Latency Estimation for ML on FPGA.
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